Analysis of the Causes of the LER Effect and Methods for Reducing Its Magnitude

Abstract This paper presents a comprehensive analysis of the sources of line edge roughness (LER) and strategies for its reduction in integrated circuit manufacturing. The main factors causing LER in the photolithographic process and the mechanisms of transferring this defect to the topology of nanostructures are identified. The correlation between the parameters of lithography, etching processes, and the final linear dimensions of IC elements is analyzed. The article discusses promising methods and technological solutions for controlling and reducing LER.