Integration of an advanced 3D TSV with the 7nm EUV logic process

The integration of a high aspect ratio Through Silicon Via (TSV) process with the EUV 7nm logic process was developed for the first time. The TSV and MOL to BEOL interface process was developed and the BEOL Via on TSV and MOL structure was evaluated. TSV to BEOL and device proximity study was performed by placing TSVs at various keep-out zone (KOZ) distances and different TSV orientations to the devices. The TSV KOZ split results for BEOL test structures showed no recognizable via/metal open/short yields loss nor performance degradation. The TSV KOZ splits results for device showed different performance variation related to both the device split parameters and TSV locations, nevertheless the variation laid within the process specification.