Wafer‐Scale High Mobility 2D Tellurium Thin‐Film Transistor for Heterogeneous Integrated 3D‐CFET Logic Circuits

Abstract Back‐end‐of‐line (BEOL)‐compatible complementary field‐effect transistor (CFET), which vertically integrates p‐channel and n‐channel thin‐film transistors (TFT) in a 3D architecture on Si‐CMOS, is critical for next‐generation electronics, enabling higher functionality and improved energy efficiency. However, the absence of a high‐performance BEOL‐compatible p‐channel TFT, the counterpart of n‐channel oxide‐TFT, continues to pose a significant challenge for the development of wafer‐scale CFET technology. Tellurium (Te) has recently emerged as a promising candidate for p‐channel TFT, but its device performance is not yet satisfactory. Here, in‐plane crystal‐oriented 2D Te channel thin‐film is successfully grown to improve its carrier transport and successfully demonstrated high mobility p‐channel Te‐TFT with high saturation mobility (≈31 cm 2 V s −1 ). The maximum process temperature is as low as 150 °C, enabling the fabrication of 3D‐vertical CFET device with heterogeneous integration with oxide‐TFTs on a 2‐inch wafer. The hybrid CFET, composed of 2D p‐Te and n‐a‐IGZO TFTs, exhibits an excellent inverter characteristic with a high voltage gain of 162 at V DD = 4 V. This study highlights the potential of low‐temperature processed p‐channel Te‐TFTs for BEOL heterogeneous‐compatible integration with oxide‐TFT technology, providing enhanced functionality and high energy‐efficiency for next‐generation electronics.