Design and implementation of a full analogue gate driver for current compensation of paralleled SiC‐MOSFETs

Abstract Silicon carbide MOSFETs have current ratings that are not sufficiently high to be used in high‐power converters. It is necessary to connect several MOSFETs in parallel in order to increase current capabilities. However, transient imbalance peak currents during turn‐on and ‐off processes challenge the performance and reliability of parallel MOSFETs. This paper considers the impact factors of device parameters, asymmetrical power circuit layout and circuit parasitic analytically to reveal the imbalance current peaks. The turn‐on and ‐off transient conditions are studied and mathematically investigated. In master‐slave configuration, a fully analogue active gate driver is designed and implemented to suppress the imbalance current among parallel silicon carbide (SiC) MOSFETs. In the proposed scheme, by exploiting an imbalance current detection circuit and I‐controller in a negative feedback for the slave MOSFET, an appropriate control voltage is obtained. The output voltage of active gate driver is adjusted by the control voltage, whether positive or negative in turn‐on and ‐off transient, in order to synchronize the peak currents of paralleled modules. Moreover, a detailed circuit of the designed compensator is presented and discussed. The experimental results are presented to verify the reliability and the effectiveness of the proposed compensator.