Projected Performance of Nanowire Transistor With Sub-1 nm Gate Length

Although gate-all-around field-effect transistor (GAAFET) possess stronger gate control capabilities compared to FinFET, continuous scaling down of the horizontal gate length remains challenging. In this work, nanowire FET (NWFET) with sub-1 nm gate length is proposed. Utilizing quantum transport approach based on density functional theory (DFT), it is verified that when gate length L_G is 0.34 nm and underlap length L_UL is 5 nm, the device meets the performance requirements for 2028 high-performance (HP) devices specified by the International Technology Roadmap for Semiconductors (ITRS). This indicates that by utilizing the lateral electric field from the side of graphene gate to control the channel and in the presence of spacer dielectric, the L_G of NWFET can be reduced to the atomic scale. Furthermore, two process schemes, namely vertical and horizontal channel configurations, are proposed for this device.