Doping‐Free Monolithic 2D CMOS Logic by Fermi‐Level Engineering via Tellurium Buffer‐Layer

2D semiconductors hold great potential for post-Moore complementary-metal-oxide semiconductor (CMOS) technology. However, the doping-free CMOS logic circuits utilizing identical 2D semiconductors pose a critical challenge in achieving efficient metal-dependent polarity modulation, predominantly due to interface defects and Fermi-level pinning (FLP) caused by metallization-induced chemical interactions. Here, a doping-free CMOS fabrication strategy is reported that employs a tellurium (Te) buffer-layer-assisted thermal deposition of the same metal to enable complementary polarity transport on the same 2D semiconductor. By introducing a sacrificial Te buffer-layer onto the 2D semiconductors prior to the thermal deposition of metal and subsequent controlled annealing for its complete removal, the created quasi-van der Waals (vdW) metal-semiconductor interface achieves work-function-dependent polarity control. This contrasts with conventional deposited contacts that lead to FLP-dominated n-type behavior. By utilizing high-work-function Au metal to modulate the polarity of the same 2D semiconductor, the fabricated CMOS inverter realizes a voltage gain of 165 at a 5 V bias and a 95% total noise margin. Importantly, this technique is readily applicable to scalable, industry-compatible CMOS devices manufacturing while concurrently optimizing interfacial charge transport characteristics, demonstrating back-end-of-line (BEOL) compatibility. This study establishes a foundational framework for 3D monolithic integration through Fermi-level engineering, paving the way for next-generation vertically integrated nanoelectronics.