Multilayer MoS2 Back‐Gate Transistors with ZrO2 Dielectric Layer Optimization for Low‐Power Electronics

Herein, high‐performance back‐gate molybdenum disulfide (MoS 2 ) field‐effect transistors (FETs) with high‐quality sub‐20 nm high‐ k dielectric layers are developed for high‐performance and lower‐power consumption applications. The 20 nm ultrathin ZrO 2 dielectric layers are deposited by thermal atomic layer deposition (ALD) method, where the growth temperature is varied and it shows a significant impact on the electrical characteristics of the deposited ZrO 2 materials. A polydimethylsiloxane (PDMS) transfer process is used to transfer multilayer MoS 2 flakes onto a 20 nm ZrO 2 /p–Si substrate with an optimized dielectric growth temperature without any subsequent processing, resulting in back‐gate MoS 2 FET device architecture. These transistors demonstrate excellent electrical characteristics with on–off current ratio up to 1.8 × 10 7 , subthreshold swing as low as 70 mV decade −1 and field‐effect mobility as high as 3.9 cm 2 V −1 s −1 . Furthermore, an enhancement‐mode device operation and a high complementary metal–oxide–semiconductor (CMOS) I ON /I OFF ratio of 10 7 are achieved. The excellent electrical performance is attributed to the low interface state traps and high‐quality ZrO 2 dielectric layer, indicating the great potential of our multilayer MoS 2 FETs technology for low‐power applications.