ON IMPLEMENTING EFFICIENT MODULO 2n + 1 ARITHMETIC COMPONENTS

It is shown that a diminished-1 adder, with minor modifications, can be also used for the modulo 2 n + 1 addition of two n-bit operands in the weighted representation, if the sum of its input operands is decreased by one. This modified diminished-1 adder can perform n-bit modulo 2 n + 1 addition in less area and time than solutions that are based on the use of binary adders and/or weighted modulo 2 n + 1 adders. Therefore, it can be applied effectively to all weighted modulo 2 n + 1 arithmetic components that finally derive two n-bit addends. A small number of weighted arithmetic components have in the past adopted such a scheme without presenting this general theory. By applying this idea, we propose novel multi-operand modulo 2 n + 1 adders (MOMAs) and residue generators (RGs). Experimental results indicate that the resulting arithmetic components offer significant savings in delay, implementation area and average power consumption compared to the currently most efficient solutions.