NMOS逻辑
PMOS逻辑
晶体管
阈值电压
CMOS芯片
炸薯条
MOSFET
电子工程
材料科学
电气工程
电压
光电子学
工程类
作者
Rafael Sanchotene Silva,Lucas Pereira Luiz,M.C. Schneider,Carlos Galup‐Montoro
标识
DOI:10.1109/tvlsi.2019.2908338
摘要
This brief describes a compact test chip in a 130-nm CMOS technology, aimed at characterizing both the short- and long-channel transistors and the series association of halo-implanted transistors. The chip contains a set of low-threshold-voltage (LVT) nMOS/pMOS transistors with several channel lengths and transistors associated in series. Parameters, such as threshold voltage, specific current, and intrinsic voltage gain, were determined through simulation and measurements of 20 chips. The results reported herein provide integrated circuit designers with guidelines for choosing either long-channel lengths or series association of transistors to comply with the requirements of their design.
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