An input buffer for 12bit 2GS/s ADC

An input buffer using in 2GS/s 12bit resolution analog-to-digital converter(ADC) is presented in this paper. The input buffer is often used in the ADC application to isolate the input signal. One of the most important design tasks of the input buffer is to suppress the non-linearity introduced by the extracted or absorbed current in the sampling circuits. In this design, a wide-band input buffer is based on the one-stage source follower structure and improved by using extra capacitors and MOS devices to suppress the non-linear current. It is supplied by the LDOs for the extra MOS devices to ensure its linear dynamic range. It consumes 70.1mW power in 2GHz sampling rate and 68.14dB SFDR at 1GHz input frequency in post simulation.