A layout design methodology using data description with correspondence between circuit and layout

Abstract Problems at present in the manual layout design of logic LSI are the high desing cost due to the overhead of detection and correction of design errors, as well as the difficulty in modifying and reusing the design data. to solve these problems, this paper proposes a data representation providing the correspondence between the circuit structure and the layout, together with a new layout design method using that idea. This data representation leads to a unified treatment based on the correspondence between the circuit data and the layout data. It is made easy to modify the design and to maintain or reuse the design data. the layout design method based on the proposed idea effectively utilizes the circuit data in the layout design, which can completely prevent routing errors, and simplifies various layout verifications. Further, this paper presents an example wherein the proposed layout design method is applied to the symbolic layout system for MOS logic LSI. the result of layout experiments indicates the usefulness of the proposed design method.