Optimization of CMOS Decoders Using Three-Transistor Logic

Decoders are among the most fundamental components in digital circuit design. They are widely used in combinational logic to convert and route binary data, as well as in memory array logic, for decoding binary addresses that point to the memory locations to be accessed. Due to their extensive utilization, optimizing decoder cells can potentially yield perceivable improvements in a digital system. This paper introduces 3-Transistor Logic (3TL), a new design approach for the optimization of CMOS decoder circuits, which combines static CMOS, Transmission-Gate Logic, and Dual-Value Logic. A complete transistor-level design methodology is demonstrated for decoder sizes from 2×4 up to 8×256, using 15 nm FinFET technology. Furthermore, an extensive comparative analysis is conducted with transistor-level simulations, evaluating the new circuits against conventional static CMOS and other previously proposed designs. The results show that 3TL circuits offer the best overall performance in terms of active power consumption, standby power consumption, and delay, owing largely to the fact that they are designed with logic efficiency and the minimum possible number of transistors.