Single‐Gate In‐Transistor Readout of Current Superposition and Collapse Utilizing Quantum Tunneling and Ferroelectric Switching

Abstract In nanostructure assemblies, the superposition of current paths forms microscopic electric circuits, and different circuit networks produce varying results, particularly when utilized as transistor channels for computing applications. However, the intricate nature of assembly networks and the winding paths of commensurate currents hinder standard circuit modeling. Inspired by the quantum collapse of superposition states for information decoding in quantum circuits, the implementation of analogous current path collapse to facilitate the detection of microscopic circuits by modifying their network topology is explored. Here, the superposition and collapse of current paths in gate‐all‐around polysilicon nanosheet arrays are demonstrated to enrich the computational resources within transistors by engineering the channel length and quantity. Switching the ferroelectric polarization of Hf 0.5 Zr 0.5 O 2 gate dielectric, which drives these transistors out‐of‐equilibrium, decodes the output polymorphism through circuit topological modifications. Furthermore, a protocol for the single‐electron readout of ferroelectric polarization is presented with tailoring the channel coherence. The introduction of lateral path superposition results into intriguing metal‐to‐insulator transitions due to transient behavior of ferroelectric switching. This ability to adjust the current networks within transistors and their interaction with ferroelectric polarization in polycrystalline nanostructures lays the groundwork for generating diverse current characteristics as potential physical databases for optimization‐based computing.