Design of a High Speed and Low Power Charge Shared Based Dynamic Comparator for ADC Application

An ultimate requirement of the less power, high speed and energy efficient analog to digital converters(ADCs) have given immense popularity to dual stage positive feedback based clocked comparators. A high speed, low power dynamic comparator is addressed in this paper. The proposed architecture is based on charge shared logic in the regenerative latch stage along with modification in the pre-amplifier stage. The power consumption has been tremendously reduced by preventing the input nodes of pre-amplifier stage from completely decreasing to ground. The delay of the circuit is also reduced compared to conventional circuits of dynamic comparator .For verification of the outcome’s, all the architectures are simulated in 45-nm technology on Cadence Virtuoso at power supply voltage of 0.8V. The new architecture of dynamic comparator consumes a total power of 1.29 μW and delay of 112.44ps at maximum operating frequency of 1GHz with 0.8V supply voltage, common mode input voltage (Vcm) of 0.7V and difference in input voltage of 5mV. The Monte Carlo analysis for various mismatch effect occurring in the circuit is also shown along with process corner analysis.