视频阵列图形
像素
帧速率
计算机科学
帧(网络)
人工智能
计算机视觉
CMOS芯片
分辨率(逻辑)
计算机硬件
图像传感器
计算机图形学(图像)
电气工程
现场可编程门阵列
工程类
电信
作者
Hirotaka Murakami,Eric Bohannon,John D. Childs,Grace Gui,Eric C. Moule,Katsuhiko Hanzawa,Tomofumi Koda,C. Takano,Toshimasa Shimizu,Yuki Takizawa,Adarsh Basavalingappa,Robert A. Childs,Cody Cziesler,R. F. Jarnot,K Nishimura,Scott Rogerson,Yoshikazu Nitta
出处
期刊:
日期:2022-02-20
卷期号:: 104-106
被引量:14
标识
DOI:10.1109/isscc42614.2022.9731607
摘要
Today's mobile devices are capable of multiple tasks, including viewing and computer vision. However, these tasks are often implemented using multiple cameras due to divergent requirements, resulting in increases in form factor. Higher resolutions and frame rates are required to take pictures and video, while lower resolutions and frame rates are preferred especially for always-on computer vision to save power. To reduce the form factor, this paper presents a single-chip solution where both high-resolution viewing images and lower-resolution computer vision images are generated from one CMOS Image sensor (CIS). Full field-of-view programmable image resolutions are made possible with floating-diffusion (FD) binning through serial switches. In-frame dynamic voltage and frequency scaling (DVFS) is applied to minimize power at lower pixel resolutions and frame rates. 1/2, 1/4, 1/8, 1/16 and 1/192 binning modes are demonstrated using a $2560(\mathsf{H})\times 1920(\mathsf{V})$ pixel array that, at 1fps, consumes $790\mu\mathsf{W}$ for full-color VGA and 120µW for motion-detection (MD) mode.
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