Design-for-Test of Asynchronous Networks-on-Chip

Thanks to many advantages, asynchronous circuits have been used to solve the interconnect problems faced by system-on-chip (SoC) designers. Some asynchronous networks-on-chip (NoCs) architectures are proposed for the communication within SoCs, but lack methodology and support for manufacturing test to ensure these communication architectures work correctly. We present an innovative asynchronous DfT architecture that allows to test the asynchronous communication network architectures, as well as the synchronous computing resources and the asynchronous/synchronous network interfaces on the asynchronous NoC-based SoCs. This asynchronous DfT architecture is implemented in quasi delay insensitive (QDI) asynchronous circuits and uses an area of about 20 * 8 Kgates in an asynchronous NoC-based SoC of 4.5 Mgates without memories.