Analytic approach to power-constrained CMOS low-noise amplifier design with figure of merit consideration

In this paper, design approach for a 5.8-GHz power-constrained CMOS low-noise amplifier using 0.13-μm process technology is presented. To evaluate the overall performance of an LNA, figure of merit (FoM) is adopted. Figure of merit includes power gain, noise figure, power dissipation and the operation frequency. Each performance factor of FoM is analytically expressed in device parameters. We show that FoM is maximized by optimizing the transistor size and bias condition. Effect of the external capacitance between the gate and the source of the input transistor for power-constrained design is explained and its influence on FoM is also discussed.