A novel salicide technology for thin film SOI MOSFETs using Ge pre-amorphization

Summary form only given. Salicide technology has been widely used to reduce the source/drain parasitic resistance of fully depleted SOI MOSFETs. However, for thinner films the design window for salicide process is narrowed due to the void formation in the interface of silicided and non-silicided source/drain regions. The key to avoid the formation of voids and to minimize dopant segregation is to lower the silicide formation thermal cycle, and/or to limit the depth of the silicide so that phase equilibrium with silicon is maintained. We propose a novel salicide technology by forming silicide on Ge-implanted S/D regions. Bandgap engineering was used to alleviate floating body effects of SOI. In this work, Ge pre-amorphization is applied to control the silicide depth by forming a sharp amorphous/ crystalline interface. The damaged S/D regions lower the silicide formation energy substantially, which allows us to use a low temperature process and helps reduce the dopant underneath the S/D side wall spacer from segregating into the silicide. It is demonstrated that Ge pre-amorphization significantly reduces the series resistance without degrading device performance.