PLAD (Plasma Doping) for p-type Deep Trench Doping in Power Device Applications

Doping high aspect ratio (HAR) structures poses a major challenge for device manufacturers, particularly in the advanced memory, CMOS image sensor technology spaces, and in the fabrication of trench based super-junction MOSFET power devices. CMOS technology scaling limitations have led to the emergence of vertically integrated cells, which leading-edge chipmakers are already introducing into mass production in multiple applications. The focus of this work is to demonstrate the capability of PLAD to dope large, but very high aspect ratio features in super-junction MOSFET power devices. PLAD has demonstrated this capability in a range of semiconductor applications including memory and image sensor processes. In this work, optimization of low dopant concentration is shown to enable high aspect ratio sidewall doping of a power device structure. Additionally, we will describe the unique capability of PLAD, results of various doping conditions, and additional new metrology capability for characterizing this process space.