Multiphysics Reliability Modeling of Flip-Chip Package Build Up Film Passivation Crack

Flip Chip (FC) packaging technology has been regarded as the de-facto standard for high performance, high volume, better reliability, smaller size, and cost-effective solutions. However, with integration and miniaturization come mechanical reliability challenges - primarily interfacial delamination and cracks. Build-up passivation film crack is typically observed under the temperature cycle (TC: −65/150C) reliability test (shown in Fig. 1). Generally, this failure mode is attributed to the marginality of the fracture strength of the complex internal and external stress interaction at the junction of the film and metal structure localized interface under TC loading. As such, assessing the cause of derisking this failure mode early in the design process is critical. This study develops a coupled thermomechanical predictive modeling methodology to capture localized stress interactions. The methodology coupled finite element analysis (FEA) and digital image correlation (DIC) techniques to model local thermal strain, due to different coefficient-of-thermal expansion (CTE), at the metal and dielectric interface. The integrity of the predictive modeling methodology was validated with empirical measurements on multiple test vehicles. The methodology developed here can be employed to predict the impact of thermomechanical reliability issues early in the design process.