A Step‐by‐Step Optimization of the c‐Si Bottom Cell in Monolithic Perovskite/c‐Si Tandem Devices

Perovskite/crystalline‐silicon (c‐Si) tandem devices are of great interest as potential candidates for next‐generation photovoltaic devices. Such devices could combine a higher efficiency than c‐Si with an acceptably low‐production cost to enable further reductions in PV system costs. To date, little attention has been paid to the optimization of the c‐Si bottom cell in these devices. However, for the highest possible efficiency, such an optimization is necessary. Here, the authors use numerical modeling to rigorously analyze the impact of doping type, doping concentration, and device architecture on the efficiency of the c‐Si bottom cell. We show that the use of low‐resistivity p‐type wafers can result in higher efficiencies than the currently favored n‐type, moderate resistivity wafers, for both homo‐ and heterojunction bottom c‐Si devices. Two new device structures – localized emitter rear localized (LERL) and reversed tunneling oxide passivating contact (rTOPCon) are proposed in order to further simplify cell fabrication and improve the device efficiency. The authors show that these structures are capable of the same high efficiencies as heterojunction cells while offering substantially greater temperature tolerance for the deposition of the perovskite top cell. The implementation of such optimized c‐Si bottom cells will be crucial to the achievement of over 30% efficient tandem devices.