Design Study of Next-Generation Hybrid Bonding Processes for Chip-Scale Integration

Hybrid bonding (HB) is a key enabler for next-generation 3D stacked LSIs; however, air-trap defects in thinned Si chips remain a critical limitation to yield and reliability. Trapped air during chip stacking degrades Cu–Cu interconnect integrity, necessitating a physics-based understanding of air-expulsion dynamics under chip warpage. In this study, a pseudo-transient "airbag method" integrated with FEM simulations is proposed to capture transient air-expulsion behavior in ultra-thin chip bonding. The proposed approach enables efficient and accurate prediction of chip deformation and interfacial air dynamics. The results reveal that chip thickness, collet curvature, and warpage are the dominant factors governing air-removal efficiency. Based on these insights, a robust process window for void-free bonding is established, providing a predictive framework for HB optimization toward high-yield 3D integration.