A Monolithically Integrated DWDM Si-Photonics Transceiver for Chiplet Optical I/O

A monolithically integrated dense wavelength-division multiplexing (DWDM) silicon photonics (SiPh) transceiver is presented. Based on the high-Q micro-ring resonation, four 200-GHz spaced wavelengths transmitting and receiving at 50 Gb/s/ $\lambda $ each are demonstrated. All necessary electronic and photonic circuits are fully integrated on a single CMOS chip, including four-channel driver (Drv), transimpedance amplifier (TIA), micro-ring modulator (MRM), micro-ring filter (MRF), and photodetector (PD). An asymmetric inductive-peaking technique is proposed in the co-designed Drv, compensating for insufficient bandwidth (BW) and dynamic nonlinearity of the MRM. To overcome process and temperature variations, closed-loop wavelength stabilization is accomplished with field-programmable gate array (FPGA) algorithm. Implemented in 45-nm silicon-on-insulator (SOI) CMOS, the experimental results show clear eyes at $4{\lambda }{\times }50$ -Gb/s transmitting and receiving, respectively, with ${\lt } 10{^{-12}}$ bit error rate (BER). At 50-Gb/s/lane speed, the proposed transceiver achieves 176 Gb/s/mm² BW density and 3.5-pJ/bit power efficiency, which is boosted to 224-Gb/s/mm² and 2.85-pJ/bit running at 64 Gb/s/lane. Full-link transceiver and multi- $\lambda $ crosstalk experiments are demonstrated at 50 Gb/s.