EMIB-T (TSV) Advanced Packaging Technology EMIB's Next Evolution

Embedded Multi-die Interconnect Bridge (EMIB) packaging technology has been being widely adopted in Intel's FPGA, Server CPU, GPU, and data centric high-performance compute (HPC) segments for heterogeneous integration (HI) applications. Recently, emerging artificial intelligence (AI) and machine learning (ML) applications have spiked the demand for hyper large form factor (HLFF) data center GPUs and CPUs with significant on-package memory bandwidth (e. g. high bandwidth memory (HBM)) to meet exploding training, inference and learning workloads. As the next evolution of EMIB, EMIB-T (TSV) advanced packaging technology enables a direct power delivery path through EMIB bridges via through silicon via (TSV), from the package bottom to HBM dies. As a result, EMIB-T technology significantly improves package power delivery efficiency, enables ultra-high speed UCIe-A die-to-die (D2D) communications, and paves the way to reach massive bandwidth density capability. In this paper, we discuss the technological considerations, and progress roadmap in enabling EMIB-T technology. In addition, we provide the process flow comparison between EMIB and EMIB-T technologies and share the unique challenges that EMIB-T technology poses with respect to equipment, materials, and integrated process. Together, EMIB and EMIB-T (TSV) packaging technologies provide a cost effective, high yielding, and elegant design alternative to future AI systems beyond existing 2.5 D industry solutions, with the scalability to ultra large area die complexes and HLFF packages in the AI era.