Signal and Power Integrity Co-Simulation of Chiplet-to-Chiplet Channel Based on Latency Insertion Method

This paper introduces a transient simulation approach for conducting signal and power integrity analysis in chiplet systems based on Latency Insertion Method (LIM). LIM is utilized to simulate the system including power distribution network (PDN), the drivers in the chips, and the interconnection between chiplets. The PDN and chip drivers are represented through equivalent circuit models. And the channels are treated as blackbox networks characterized by scattering parameters, and are incorporated to LIM through macromodeling. The proposed method is capable of providing transient analysis results, including on-chip voltage fluctuations induced by the PDN and signal propagation through the inter-chiplet channels. It can demonstrate how imperfections in the PDN can impact signal integrity, offering valuable insights for optimizing system in package (SiP) design.