Chip level layout and bias considerations for preventing neighboring I/O cell interaction-induced latch-up and inter-power supply latch-up in advanced CMOS technologies

CMOS latch-up has historically been a problem in bulk CMOS processes through a parasitic pnpn structure formed by parasitic pnp and npn bipolar transistors. In application systems, latch-up is a dominant failure mode that causes either soft failure due to a loss of data logic states or destructive failure of the system. In this paper, the authors focused on cases of I/O VDD to core VDD latch-up and other cross book latch-up; the significance of this work shows that in 0.13 and sub-0.13 mum technologies, CMOS latch-up can occur between different VDD power supplies and between chip sub-functions. This work advances the CMOS technology by addressing chip-level layout, critical bias considerations, as well as and in conjunction with unit I/O cell level latch-up considerations for preventing neighboring I/O-to-I/O cell interaction-induced latch-up. Additionally, emission microscope (EMMI) techniques and latch-up simulation results were shown.