作者
D. Ingerly,Kabir Enamul,Wilfred Gomes,Derick Jones,Kalyan C. Kolluru,A. Kandas,G.-S. Kim,Huimin Ma,D. Pantuso,Cole Petersburg,M. Phen-givoni,Sally Safwat Amin,Anuradha Pillai,Ashok Singh Sairam,P. Shekhar,Pankaj Sinha,Patrick Stover,Aditya Telang,Z. Zell,L. Aryasomayajula,Ajay Balankutty,Donny de Borst,Anshuman Chandra,Krishnayya Cheemalapati,Charles F. Cook,R. Criss
摘要
This paper presents the key silicon features of Intel’s 3D stacking technology, Foveros, as it is used to enable logic-on-logic die stacking. A robust face-to-face die connection is enabled with a high yielding, robust microbump connection. Additionally, we describe the low resistance TSVs used for connection to the package along with their electrical properties.