极紫外光刻
节点(物理)
缩放比例
工程类
计算机科学
电信
物理
光电子学
数学
结构工程
几何学
作者
Ryan Ryoung-Han Kim,Syed Muhammad Yasser Sherazi,Peter Debacker,Praveen Raghavan,Julien Ryckaert,Arindam Malik,Diederik Verkest,Jae Uk Lee,Werner Gillijns,Ling Ee Tan,Víctor Blanco,Kurt Ronse,Greg McIntyre
摘要
In order to maintain the scaling trend in logic technology node progression, imec technology nodes started heavily utilizing design technology co-optimization (DTCO) on top of loosen pitch scaling trend to mitigate the burden from steep cost increase and yield challenge. Scaling boosters are adopted to enable DTCO process on top of patterning near its cliff to mitigate the cost increase. As the technology node further proceeds, DTCO also starts facing its cliff, and system technology co-optimization (STCO) is introduced to assist pitch and DTCO scaling to bridge 2-D IC technology to evolutionary technology options such as MRAM, 2.5-D heterogeneous integration, 3-D integration and 3-D IC. EUV is used to further assist pitch and DTCO scaling to maintain low cost with higher yield and faster turn-around-time (TAT). EUV single patterning, multiple patterning and high-NA EUV are considered on top of DTCO and STCO landscape to define imec technology nodes.
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