Modeling and control of resistance tolerance for embedded resistors in LTCC

For embedded resistors in LTCC, the challenge is the high resistance tolerance, normally 20/spl sim/30%. This paper is aimed at modeling and reduction of the tolerance to meet the requirements for high frequency applications; less than 10% resistance tolerance. A mathematical equation for resistance tolerance was derived and experimentally validated. The predicted resistance tolerance agrees with the measured value. With the aid of this equation, resistance tolerance can be related to the tolerance of the print geometry, which is measurable and adjustable prior to firing. It is predicted that for the 10% resistance tolerance goal, print thickness tolerance must be no more than 8%. A comprehensive analysis and step-by-step strategy for tolerance reduction is presented in this work. Some experimental studies have been performed to determine the major factors affecting tolerance. Non-process related factors include resistor size (width and aspect ratio), number of resistor layers in the substrate, location of the resistors on a layer, and printer set-up. As for processing, if the printing is performed in a period of 7 to 17 minutes after paste is applied on the screen, consistent print geometry can be obtained. In addition, a 3-level and 5 factors design of experiments (DOE) shows that the printing parameters, except the low level of squeegee travel, have no significant effect on tolerance of print thickness and width. These results indicate that tolerance control must begin with the design, and include an optimized printer set-up for uniform print thickness across a large printed area. In addition, an appropriate printing process must be used to obtain high resolution rectangular resistors. Through these efforts, 6% to 10% thickness tolerance have been achieved for various print runs and process combinations. Further experiments are underway to evaluate tolerances from high volume production.