Research and Design of RISC-V Four-Stage Out-of-Order Execution Processor

Research on embedded processors based on the RISC-V instruction set, most of the research focuses on small-scale processors with sequential execution and 2-3 stage pipelines in performance evaluation. To solve this problem, this paper proposes a four-stage pipeline structure with sequential launch, out-of-order execution, and out-of-order write-back. Based on the four-stage pipeline architecture, this paper designs a 32-bit low-power high-performance processor based on the open-source RISC-V instruction set, which supports RISC-V basic integer operations, multiplication and division, and proposes optimization schemes for instruction prediction respectively. The logic function of the processor is verified in the Vivado environment, and the designed Dhrystone has a running score of 1.28DMIPS/MHz, which is better than most of the open-source processor cores.