The Trapping Mechanism at the AlGaN/GaN Interface and the Turn-On Characteristics of the p-GaN Direct-Coupled FET Logic Inverters

The trapping mechanism at the AlGaN/GaN interface in the p-GaN high electron mobility transistors (HEMTs) and its impact on the turn-on characteristics of direct-coupled FET logic (DCFL) inverters were investigated across various supply voltages (V_DD) and test frequencies (f_m). The frequency-conductance method identified two trap states at the AlGaN/GaN interface (trap activation energy E_c-E_T ranges from 0.345 eV to 0.363 eV and 0.438 eV to 0.47 eV). As V_DD increased from 1.5 V to 5 V, the interface traps captured more electrons, increasing the channel resistance (R_channel) and drift-region resistance (R_drift) of the p-GaN HEMTs and raising the low-level voltage (V_OL) from 0.56 V to 1.01 V. At f_m = 1 kHz, sufficient trapping and de-trapping led to a delay of 220 µs and a V_OL instability of 320 mV. Additionally, as f_m increased from 1 kHz to 200 kHz, a positive shift in the threshold voltage of p-GaN HEMTs occurred due to the dominance of trapping. This shift caused V_OL to rise from 1.02 V to 1.40 V and extended the fall time (t_fall) from 153 ns to 1 µs. This investigation enhances the understanding of DCFL GaN inverters' behaviors from the perspective of device physics on power switching applications.