A 25–32-GHz Frequency Doubler With 21% Efficiency and 41-dBc Fundamental Rejection

This brief presents a frequency doubler operating in the 25-32 GHz range with high fundamental rejection in the 130 nm SiGe BiCMOS process. The inductor connected to the base of common emitter transistor contributes to the harmonic reflector and input impedance matching. The output multi-frequency filter network (OMFN) suppresses the fundamental and the fourth harmonic. The measured results show that the frequency doubler achieves 3-dB gain bandwidth of 7 GHz (25-32 GHz). At an input power of 0 dBm, the proposed frequency doubler exhibits a fundamental rejection of 41 dBc and a DC power consumption of 22 mW. The second harmonic peak PAE is 20% and the peak η is 21%. The doubler occupied an area of 0.52 mm2 including all test pads.