Area-Time Efficient Hardware Design for Crystals-Dilithium

CRYSTALS-Dilithium (Dilithium), a digital signature scheme based on lattice cryptography, has recently been designated as a standard for post-quantum digital signatures by the National Institute of Standards and Technology. Known for its strong security guarantees and efficient use of polynomial arithmetic, Dilithium offers a promising foundation for futureproof digital signatures. However, implementing such latticebased schemes in hardware introduces significant challenges due to the high computational demands and structural complexity of their core operations. To overcome these issues, this work focuses on optimizing Dilithium for field-programmable gate arrays (FPGAs), which offer substantial potential for performance gains through parallelism and customized architectural design. We introduce a novel hardware design that improves performance and area by employing a $2 \times 2$ butterfly number-theoretic transform capable of computing two transform stages per cycle, along with a conflict-free memory subsystem that leverages pipelined coefficient rearrangement and an address resolution mechanism to ensure continuous data access. Evaluation on an Xilinx Versal Premium FPGA shows that our design enhanced resource utilization and performance, reaching 328 MHz and an area-time product of $\mathbf{5. 4}$ KLUTs $\times \mathbf{m s}$ at security level $\mathbf{2}$.