3D SRAM Using Ultrathin Body Nanosheets and Bitline Signal Decoupling

The heterogeneous vertically stacked 4T/2T SRAM is optimized using buried power rails and buried signal rails. The bitcell area of 3D SRAM can be reduced by 28% compared to 6T SRAM without transistor stacking. SRAM performance is improved by increasing nanosheet nFET floor numbers without minimum operating voltage degradation. Ultrathin bodies can reduce parasitic capacitance thanks to the total gate metal height reduction. Bitline signal decoupling can reduce read time by 12%. 166ps read time and 65ps write time can be achieved with 5nm of body thickness, 25nm of nanosheet width, and floor number = 5. With 3nm of body thickness, read and write time are further reduced by 5% and 8%, respectively, even with 13% low-field mobility degradation.