Time and frequency domain analysis of integral decoupling capacitors

Decoupling capacitors have been designed and included in high-speed packaging systems to avoid voltage drops across the power supply caused by interconnect inductance. They are also used to reduce simultaneous switching noise between the power supply and device I/O buffers. This paper will review three different measurement methods by which these capacitors were analyzed. It will discuss the possible detriments when making both low frequency and high frequency measurements on electronic packages and surface mount chip components using commercial instruments and fixtures. Two different types of high performance electronic packages with integral decoupling capacitors were analyzed. The models derived from the measurements were included in a circuit simulation to determine the effectiveness of decoupling noise between the device drivers and the system power supply. The results will provide insight into the effectiveness or these types of capacitors used within a high-speed electronic system.