An All-Region BSIM Thin-Film Transistor Model for Display and BEOL 3-D Integration Applications

This article introduces a compact model for single-gate and multigate thin-film transistors (TFTs) based on the Berkeley short-channel IGFET model-common multiple gate (BSIM-CMG) framework, valid in all regions of TFT operation. We develop a model for the channel charge density, including the impact of traps in the amorphous/polycrystalline channel of TFT, based on a linear potential profile approximation along the gate-normal direction. We further develop explicit, charge-based compact models for current and terminal charges. Unlike previous models, this model implicitly includes the impact of trap-limited conduction mechanism. In addition, we include the impact of Schottky source/drain contact resistances and temperature dependencies. The model is carefully validated with published experimental data of TFTs using diverse channel materials, including oxide semiconductors (OSs) and poly-Si, and various geometries, spanning applications in displays and emerging 3-D back-end-of-line (BEOL) integration scenarios.