Organic Nonvolatile 2T Memory Cell Employing a NOT‐Gate‐Like Architecture Toward Binary Output Level With Enhanced Noise Tolerance

Abstract Organic nonvolatile memory has been considered a low‐cost memory technology for flexible electronics and Internet‐of‐things (IoT). However, a major concern is the nonuniformity of memory units, which is primarily caused by random grain boundaries, interface defects, and charge traps, making it difficult to develop high‐density reliable memory arrays. This nonuniformity problem would induce read error, which is directly caused by the narrow distribution margin of memory states and low noise tolerance in conventional organic memory cells. To break this limitation, a novel 2T memory cell employing a NOT‐gate‐like architecture achieving self‐enhancing noise tolerance is presented. This unique cell consists of a pair of commonly‐gated memory transistors with contradictory “write‐and‐erase” features. It functions as a voltage divider, producing a well‐distinguished binary voltage output capability. The concept and design model of this brand‐new 2T memory cell is thoroughly discussed. It is originally characterized by noise‐tolerant memory cells irrespective of device nonuniformity. The noise tolerance range of this 2T memory cell is also investigated. The binary voltage‐readable memory state with a large noise tolerance range is obtained. Moreover, the conceptual design of the 1T2T FeRAM cell is further developed for low‐cost voltage‐readable memory technology in wearable electronic applications.