宽带
部分带宽
带宽(计算)
分路器
邻道功率比
dBc公司
电气工程
电子工程
工程类
物理
电信
放大器
光学
CMOS芯片
射频功率放大器
带通滤波器
作者
Luca Piazzon,Rocco Giofrè,Paolo Colantonio,F. Giannini
标识
DOI:10.1109/lmwc.2013.2281413
摘要
This letter presents the design and characterization of a novel wideband Doherty architecture. Both input splitter and output combiner are realized by means of two-sections branch-line alike couplers. The realized prototype based on commercial GaN active devices showsmore than 36% of fractional bandwidth, from 1.67 to 2.41 GHz. In this frequency range, the measured drain efficiency is within 59% and 43% at 6 dB of output power back-off and within 72% and 53% at saturation, with an output power around 41 dBm. More than 47% average efficiency and less than 40 dBc adjacent channel power ratio are measured applying a 20 MHz LTE digitally pre-distorted signal when the average output power is around 4 W.
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