A 4-24 Gb/s/wire Single-Ended NRZ Die-to-Die Transceiver with Low Latency for UCle Standard Package in 4nm FinFET

Ever-growing demands for data center, high performance computing (HPC) and artificial intelligence (AI) lead to strong requirement of high bandwidth memory with cost effective design on power and area. However, design with single digit nanometer processes and monolithic integration leads to higher yield loss. Chiplet design, which implements multiple dies on the same package, has become a solution to mitigate these difficulties. Recently, Universal Chiplet Interconnect Express (UCle) was released to interface partitioned dies and heterogeneous chiplet solution [1]. This paper presents a single-ended NRZ transceiver compliant with UCle Standard Package application. The proposed die-to-die transceiver support from $4-24 \mathrm{~Gb} / \mathrm{s} /$ wire and achieving up to $672 \mathrm{~Gb} / \mathrm{s} / \mathrm{mm}$ shoreline bandwidth fabricated in 4 nm FinFET.