Chip package-system co-design

To ensure that the system and chip work together, chip and system designers must provide the necessary models to one another during the design and verification stage. In this work, the issues in designing a chip-package-system are discussed and shown. Design techniques used to reduce power dissipation at 65 nm and below may negatively affect the system power supply. These issues can be avoided if chip designers provide a chip power model (CPM) to system designers.