Quick response circuit for low-power LDO voltage regulators to improve load transient response

In this work, we propose a quick response circuit to improve the load transient response of fully low dropout voltage linear regulator (LDO) which is operable with a very low power consumption. Simulating by HSPICE with 0.35 mum CMOS technology shows that we can achieve the transient responses with less transient overshoot or undershoot when driving large current loads. Comparing to the generic LDO, for example, in case of 1 muF decoupling capacitor, about 95% output drop and 27% settling time for 0.1 mA to 100 mA load current and 88% output overshoot and 63% settling time for 100 mA to 0.1 mA load current have been together improved. The proposed circuit only dissipates low static power, so we could achieve the above LDO with only 3.3 muA consuming current at V out + 1 V and 150 mA load current. V out is the output voltage of the regulator.