功率因数
总谐波失真
电气工程
工程类
电子工程
控制理论(社会学)
电压
计算机科学
控制(管理)
人工智能
作者
Xun Gong,Gangyao Wang,Manish Bhardwaj
标识
DOI:10.1109/apec.2019.8722110
摘要
This paper presents the design and performance of a 6.6kW, three-phase interleaved, high density Totem Pole (TTPL) Power Factor Correction (PFC) based on SiC MOSFETs. The converter is operated at 100 kHz and in Continuous Conduction Mode (CCM). Key design features, components selection, and control scheme are discussed in detail. The digital controller enables phase shedding and adaptive dead-time control to improve the efficiency and power factor at light load. The SiC isolated gate driver is designed to have 4 A peak and 6A sink current and contains the two-level turn-off circuit for short-circuit protection. Experimental results from the 6.6kW design show that very high peak efficiency of 98.9%, and less than 2% THD are achieved at high line (240 V) AC input with 400 V DC output.
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