Modeling of a tunable memory device made with a double-gate MoS2 FET and graphene floating gate

Electronic devices comprising low-temperature processed 2D materials can be utilized in back-end-of-line nonvolatile memory and logic applications, to augment conventional silicon technology. A promising structure for a low-temperature processed digital nonvolatile flash memory device and/or logic device is the double-gate MoS2 FET with a graphene floating gate and a thin h-BN gate dielectric serving as a tunneling dielectric. In this work, we show that experimental hysteretic current–voltage characteristics of this digital flash memory device can be well fit by a simple and effective physics-based model using a WKB approximation to calculate the tunneling current to the graphene floating gate and a capacitive network with 2D density-of-states to calculate the channel current flowing in the MoS2 channel. Accordingly, the model allows a device designer to predict and/or tune characteristics for this memory device, e.g., the width and center-position of the hysteresis loop as well as the value of source–drain current, as a function of both the bottom (control) gate and top (FET) gate voltages. It is noted that shifting of the center-position of the hysteresis loop enables improved reliability and functionality of the memory device in circuit applications and is a unique feature of this double-gated MoS2 FET. Overall, the demonstrated ability to well model this memory device lends further credence that 2D devices could augment silicon technology.