Fermi-level pinning-free WSe2 transistors via 2D van der Waals metal contacts and their complementary logic gate circuits

Abstract Precise control over the polarity of transistors is a key necessity for the construction of complementary metal–oxide–semiconductor circuits. However, the polarity control of two-dimensional (2D) transistors remains a challenge because of Fermi-level pinning resulting from disorders at metal–semiconductor interfaces. Here, we propose a strategy for clean van der Waals contacts, wherein a metallic 2D material, chlorine-doped SnSe 2 (Cl–SnSe 2 ), is used as the contact to provide an interface that is free of defects and Fermi-level pinning. Such clean contacts created via van der Waals integration of a 2D metal possess nearly ideal Schottky barrier heights, thus permitting polarity-controllable transistors. With the integration of 2D metallic Cl–SnSe 2 as contacts, WSe 2 transistors exhibit pronounced p-type characteristics, which are distinctly different from those of the devices with evaporated metal contacts, where n-type transport is observed. Finally, this ability to control the polarity enables the fabrication of functional logic gates and circuits, including inverter, NAND, and NOR.