电磁干扰
材料科学
电磁干扰
寄生元件
绝缘栅双极晶体管
电气工程
减刑
光电子学
碳化硅
噪音(视频)
dBc公司
电感
电磁屏蔽
电压
工程类
计算机科学
CMOS芯片
复合材料
图像(数学)
人工智能
作者
Asif Imran Emon,Zhao Yuan,Abdul Basit Mirza,Amol Deshpande,Mustafeez Ul Hassan,Fang Lin Luo
标识
DOI:10.1109/tpel.2021.3089578
摘要
Three-level (3L) inverters suffer from higher parasitic inductance due to the increased number of series-connected switches in a single current commutation loop (CCL) results in a larger size of CCL compared to their two-level (2L) counterparts. As such, semiconductors are subjected to higher voltage stress and severe ringing at the switching transient. While silicon carbide's (SiC) faster switching speed improves overall efficiency by reducing switching loss, the faster voltage, and current gradient (dv/dt and di/dt) generate electromagnetic interference (EMI) noise, requiring a larger and complicated filter stage design. To solve this problem, an optimized 3L T-type neutral point clamped power module has been proposed with a hybrid combination of the switch (SiC mosfet + Si IGBT) rated for 1200 V/160 A. Two direct bonded copper (DBC) substrates have been stacked to have a vertical power loop using laser-drilled vias, which provides low commutation loop inductance as low as 4.6 nH for the major CCLs including the wire bond. Other associated CCLs have also been identified and optimized. Additional DBC in the package will be acting as an EMI shield. The EMI noise has been compared to a traditional power module and a 21 dB reduction of common-mode noise has been observed.
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