A 1.2-ns Delay Level Shifter Circuit Using Multiple Fast Charging, Discharging, and Feed-Forward Paths

This paper presents a new high-speed, low-power level shifter circuit capable of converting low-voltage input pulses to high-voltage output pulses with minimal propagation delay and dynamic power consumption. The proposed architecture leverages fast feed-forward, charging and discharging paths to enhance speed and energy efficiency, making it suitable for high-performance and high-speed applications such as system-on-chip (SoCs), high-speed memories, and FPGAs. Implemented in 130 nm TSMC CMOS technology, the circuit supports input voltages ranging from 200 mV to 0.8 V and converts them to a 1.2 V output. It achieves propagation delays of 1.19 ns and 0.34 ns for input voltages of 0.3 V and 0.4 V, respectively. The level shifter exhibits low energy consumption, with average energy per transition measured at 16.22 fJ and 14.92 fJ for 0.3 V and 0.4 V inputs, respectively. The total silicon area of the circuit is 49.4 μm². We show that the presented design outperforms recent solutions.