Study of Vth Degradation Mechanism in FeFET with TiN/Al2O3/HfO2/Al2O3/Hf0.5Zr0.5O2/SiOx/Si Structure

In this work, we investigate the degradation of the threshold voltage after erasing operation in $\mathbf{HfO}_{2}$. -based ferroelectric silicon channel field-effect transistors ($\mathbf{HfO}_{2}$ SiFeFETs) with a $\text{TiN} / \text{Al}_2 \mathrm{O}_3 / \text{HfO}_2 / \text{Al}_2 \mathrm{O}_3 / \text{Hf}_{0.5} \text{Zr}_{0.5} \mathrm{O}_2 / \text{SiO}_{\mathrm{x}} / \text{Si}$ (MAHAFIS) structure. We found that the de-trapping of charges injected from the metal gate is the main factor for the degradation. Moreover, the concentrated distribution of trap energy levels exacerbates this issue. This differs from the FeFET with the $\mathbf{T i N} / \mathbf{H f}_{0.5} \mathbf{Z r}_{0.5} \mathbf{O}_2 / \mathbf{S i O}_{\mathbf{x}} / \mathbf{S i}$ (MFIS) structure, where the degradation is due to the increased trapped charges injected from the silicon substrate. Therefore, for FeFET with a top interlayer, increasing deep level traps and reducing charge detrapping is crucial to suppress the degradation of the threshold voltage after erasing operation.