A 65nm Cryogenic CMOS Design and Performance at 4.2K for Quantum State Controller Application

A performance evaluation of cryogenic CMOS circuit at liquid-helium temperature (4.2K) is conducted using a standard 65nm bulk CMOS for quantum state controller (QSC) applications. The ON-current (Ion) of the core n/pMOSFET are increased by 25% and 9% with excellent gate modulation (Ion/Ioff= $\sim 10~^{\mathrm{ 9}}$ ). The cryogenic characteristics of copper interconnects in the back end of the line (BEOL), including line and via resistances, capacitances, and Joule-heating effect (JHE) are accurately assessed. The interconnect and via resistances decrease with temperature due to a reduction of electron-phonon scattering, resulting in resistances that are 75% and 20% lower at 4.2K compared to those at room temperature(RT). No significant change in inter-line capacitance and no severe JHE are observed in the Cu BEOL at 4.2K. The developed cell libraries for Simulation Program with Integrated Circuit Emphasis (SPICE) model and the technology file, which includes RC interconnect parameters, enable precise design of CMOS circuits at 4.2K. This results in a demonstrated +18.3% increase in speed or −16% reduction in power consumption for ring-oscillator (ROSC) at 4.2K, aligning well with the simulation results obtained from the developed model.