50Gb/s high-speed serial interface receiver CTLE equalization circuit design

In high-speed interface circuits, a continuous-time linear equalizer (CTLE) is typically used at the receiving end to eliminate the effect of intersymbol interference (ISI) on signal transmission. In order to improve the shortcomings of traditional CTLE, such as limited single-stage compensation ability and excessive layout area caused by the use of large capacitors, a two-stage CTLE circuit is designed. The first stage CTLE adopts a transconductance cascade transimpedance (TAS-TIS) structure, consisting of two parts: a high-pass transconductance amplification (Gm-HF) circuit and a transimpedance amplifier (TIA) circuit. The GM-HF circuit uses active inductance as load and source-level negative feedback network and other technologies, which can effectively expand the operating frequency of the circuit without adding additional power consumption, while saving the area of the layout. The TIA circuit uses a transimpedance amplifier structure based on an inverter unit, which uses voltage-current feedback to reduce the input resistance value and increase the input bandwidth of the signal. The second stage CTLE adds a feed-forward path between the input transistor and the inductor, thereby increasing the gain lift of the circuit without affecting the gain of the low frequency. The simulation results show that the eye diagram eye width of the 40Gbps PAM4 (four-level pulse amplitude modulation) signal, 50Gbps PAM4 signal and 28Gbps NRZ (non-return-to-zero code) signal after equalization reaches 0.68/0.5/0.92 code element intervals (UI), respectively, and the eye height reaches 280/200/690 mV.