2-V/100-ns 1T/1C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and nonrelaxation reference cell

Nonvolatile memory embedded in microcontrollers has required a 100 ns access time at 2.0 V for mobile information terminals operating with a rechargeable battery. To achieve this, this paper proposes a new ferroelectric nonvolatile memory (FeRAM) architecture that utilizes a bitline-driven read scheme and a nonrelaxation reference cell for high-speed and low-voltage operations, respectively. Using this architecture, FeRAM with a one transistor and one capacitor per bit (1T/1C) cell can achieve 100 ns access time at 2.0 V.